DESIGNING METHOD OF DATA PROCESSING SYSTEM, DESIGN ASSISTING DEVICE, AND VERIFYING METHOD

摘要

A subject bus system receives casting data at a regular interval and carries out a pipe-line-like operation. In order to take out real time restrictions to each circuit module in compliance with latency and throughput restrictions given as a specification, circuit-module level operations of the bus system are described with a sub-class of a time Petri net, the worst execution time of a bus transfer is then estimated and the time Petri net is analyzed by using its value. In its analysis, the real time restrictions are taken out by subtracting the maximum limit or the worst possible waiting time due to bus conflicts or resource conflicts between the circuit modules. Thus, when the bus system is designed to satisfy the real time restrictions given as a demand specification, the real time restrictions for each circuit module constituting the bus system can be estimated as precisely as possible at an early stage.