Strategy for integer-N frequency Synthesis using Limited Delay Stages

摘要

The present invention relates to a DL-based frequency synthesis, and in particular, by passing the input clock through the number of annular variable delays corresponding to a predetermined synthesis coefficient, an output clock having a synthesized frequency that is twice the synthesis coefficient compared to the reference clock is obtained. The present invention relates to a DL-based frequency synthesizing apparatus and method using an annular variable delay device.;The present invention does not have a variable delay stage proportional to the conventional frequency synthesis coefficient N, and can minimize the burden of hardware since the frequency can be synthesized by repeating operation by providing only an even number of unit delay stages in a ring shape. It is a DL-based frequency synthesizing apparatus and method using an annular variable delay. The present invention is a DL-based frequency synthesizer using a method of interpolating using a phase of a clock in a plurality of unit delay stages having a ring-shaped variable delay unit using the same even number of unit delay stages. It has the advantage of jitter compared to the base frequency synthesizer.;Frequency synthesizer, variable delay, synthesis coefficient,