SIMULATION METHOD AND APPARATUS AT GATE LEVEL, METHOD OF DESIGING ICS, METHOD OF DESIGNING ICS INCLUDING VOLTAGE ISLANDS, AND METHOD OF DESIGNING CHIPS

摘要

A dynamic simulation method in a gate level, a simulation apparatus of the gate level, a design method of an IC(Integrated Circuit), a method for designing an IC chip including a voltage island and a chip designing method are provided to acquire exact simulation results from a multi voltage design or a power gating design by performing simulation in consideration of variable power and ground states. A net-list is provided, wherein the net-list includes the information on variable power and ground(S110). A circuit model including the variable power and ground is provided(S120). A simulation is performed on the net-list by using the circuit model(S130). The results of the simulation are changed according to the states of power or ground. The simulation is performed by using a Verilog HDL(Hardware Description Language).