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DEVICE error detection and correction in the codes of polynomial system of residue class BASED NULEVIZATSII

机译:基于残基类NULEVIZATSII的多项式系统代码中的DEVICE错误检测和纠正

摘要

1.the device u043eu0431u043du0430u0440u0443u0436u0435u043du0438u00a0 and error correction code system in u043fu043eu043bu0438u043du043eu043cu0438u0430u043bu044cu043du043eu0439 deductions on the basis of u043du0443u043bu0435u0432u0438u0437u0430u0446u0438u0438 u043eu0442u043bu0438u0447u0430u044eu0449u0435u0435u0441u00a0 classes, so that the device contains the entrance to u043eu0442u043eu0440u044bu0439 is connected to the inputs of u043du0443u043bu0435u0432u0438u0437u0430u0446u0438u0438, building block u043du0443u043bu0435u0432u0438u0437u0430u0446u0438u0438 connected to u0432u0445u043eu0434u0430u043c block u043fu0430u043cu00a0u0442u0438 exits which are connected to the second u0432u0445u043eu0434u0430u043c, seven u043au043eu0440u0440u0435u043au0442 u0438u0440u0443u044eu0449u0438u0445 u0441u0443u043cu043cu0430u0442u043eu0440u043eu0432 entrances which are connected with the first gate devicethe corrective u0441u0443u043cu043cu0430u0442u043eu0440u043eu0432 u00a0u0432u043bu00a0u044eu0442u0441u00a0 exit device, u0434u043bu00a0 correction result u0432u044bu043fu043eu043bu043du00a0u0435u0442u0441u00a0 parallel subtraction constants u043du0443u043bu0435u0432u0438u0437u0430u0446 modified ai, as well as u043fu0440u0438u043cu0435u043du00a0u0435u0442u0441u00a0 u043du0435u0439u0440u043eu0441u0435u0442u0435u0432u043eu0439 basis.;2. device for p.1, u043eu0442u043bu0438u0447u0430u044eu0449u0435u0435u0441u00a0, block u043du0443u043bu0435u0432u0438u0437u0430u0446u0438u0438 u043fu0440u0435u0434u0441u0442u0430u0432u043bu00a0u0435u0442 a u0434u0432u0443u0445u0441u043bu043eu0439u043du0443u044e neural network, the first layer, which contains 31 neuron, and the second layer u0434u0435u0441u00a0u0442u044c neurons, but u043eu043bu043du00a0u044eu0449u0438u0445 u0441u0443u043cu043cu0438u0440u043eu0432u0430u043du0438u00a0 basic operation module, where the first, second u0441u043bu043eu00a0 neuron connected to the outputs of neurons 2, 8, 9, 11, 13, 14, 21, 22 on the first u0441u043bu043eu00a0, entrances w the second u0441u043bu043eu00a0 u043eu0440u043eu0433u043e neuron connected to the outputs of neurons 29, 10, 12, 14, 15, 17, 23, the first u0441u043bu043eu00a0 neurons, where the second u0441u043bu043eu00a0 third neuron connected to the outputs of neurons 1, 4, 7, 10, 14, 16, 18, 24 neurons first u0441u043bu043eu00a0, entrance 4 her ron's second u0441u043bu043eu00a0 connected to outputs of neurons (5, 7, 9, 11, 12, 19, 21, 25 neurons first u0441u043bu043eu00a0, entrances u043fu00a0u0442u043eu0433u043e second u0441u043bu043eu00a0 neuron connected to the outputs of neurons (6, 7, 8, 10, 12, 13. 20, 26 on the first u0441u043bu043eu00a0,the second u0441u043bu043eu00a0 entrances of neuron connected to the outputs of neurons 2, 9, 11, 13, 18, 19, 20, 27 on the first u0441u043bu043eu00a0, entrances of the second u0441u043bu043eu00a0 neuron connected to outputs neurons, 3, 10, 12, 14, 17, 19, 20, 28, the first u0441u043bu043eu00a0 neurons, where the second u0441u043bu043eu00a0 eighth neuron is connected to outputs of neurons (4, 7, 9, 12, 15, 19, 20, 29, the first u0441u043bu043eu00a0 neurons.the second u0441u043bu043eu00a0 entrances u0434u0435u0432u00a0u0442u043eu0433u043e neuron is connected to the outputs of neurons 1, 5, 7, 8, 9, 10, 13, 14, 15, 16, 18, 19, 20, 30 on the first u0441u043bu043eu00a0, entrances u0434u0435u0441u00a0u0442u043eu0433u043e neuron is connected to the second u0441u043bu043eu00a0 outputs of neurons (6, 8, 10, 11, 12, 16, 17, 18, 20, 31 on the first u0441u043bu043eu00a0.
机译:1.设备 u043e u0431 u043d u0430 u0440 u0443 u0436 u0435 u043d u0438 u00a0和 u043f u043e u043b u0438 u043d u043d u043e u043c u0438 u0430中的错误纠正代码系统 u043b u044c u043d u043e u0439推导基于 u043d u0443 u043b u0435 u0432 u0438 u0437 u0430 u0446 u0438 u0438 u043e u0442 u043b u043b u0438 u0447 u0430 u044e u0449 u0435 u0435 u0441 u00a0类,以便设备包含 u043e u0442 u043e u0440 u044b u0439的入口连接到 u043d u0443 u043b u043b u0435 u0432 u0438 u0437 u0430 u0446 u0438 u0438,构件 u043d u0443 u043b u0435 u0432 u0438 u0437 u0430 u0430 u0446 u0438 u0438已连接到 u0432 u0445 u043e u0434 u0430 u043块 u043f u0430 u043c u00a0 u0442 u0438出口与第二个 u0432 u0445 u043e u0434 u0430 u043c,七个 u043a u043e u0440 u0440 u0440 u0435 u043a u0442 u0438 u0440 u0443 u044e u0449 u0438 u0445 u0441 u0443 u043c u043c u0430 u0442 u043e u0440 u043e u0432与入口相连的入口第一门设备校正 u0441 u0443 u043c u043c u0430 u0442 u043e u0440 u043e u0432 u00a0 u0432 u043b u00a0 u044e u0442 u0441 u0431 u00a0退出设备, u0434 u043b u00b0结果 u0432 u044b u043f u043e u043b u043d u00a0 u0435 u0442 u0441 u00a0并行减法常量 u043d u0443 u043b u0435 u0432 u0438 u0437 u0430 u0446修改的ai以及 u043f u0440 u0438 u043c u0435 u043d u00a0 u0435 u0432 u0442 u0441 u00a0 u043d u0435 u0439 u0440 u043e u0441 u0435 u0435 u0442 u0435 u0432 u043e u2439 。第1页的设备, u043e u0442 u043b u0438 u0447 u0430 u044e u0449 u0435 u0435 u0441 u00a0,块 u043d u0443 u043b u0435 u0435 u0432 u0438 u0437 u0430 u0446 u0438 u0438 u043f u0440 u0435 u0434 u0441 u0442 u0430 u0432 u043b u00a0 u0435 u0442一个 u0434 u0432 u0443 u0445 u0441 u043b u043e u0439 u043d u043d u044e神经网络,第一层包含31个神经元,第二层 u0434 u0435 u0441 u00a0 u0442 u044c神经元,但 u043e u043b u043d u00a0 u044e u0449 u0438 u0445 u0441 u0443 u043c u043c u0438 u0440 u043e u0432 u0430 u043d u0438 u00a0基本操作模块,其中第一个,第二个 u0441 u043b u043e u00a0神经元连接到神经元2、8的输出第一个 u0441 u043b u043e u00a0的9、11、13、14、21、22,第二个 u0441 u043b u043e u00a0 u043e u0440 u043e u0433 u043e的入口处第29、10、12、14、15、17、23个神经元,第一个 u0441 u043b u043e u00a0神经元,其中第二个 u0441 u043b u043b u043e u0030 o神经元1、4、7、10、14、16、18、24个神经元的输出,第一个 u0441 u043b u043e u00a0,入口4她的第二个 u0441 u043b u043e u00a0连接到神经元的输出( 5,7,9,11,12,12,19,21,25个神经元连接的第一个 u0441 u043b u043e u00a0,入口 u043f u00a0 u0442 u043e u0433 u043e第二个 u0441 u043b u043e 到神经元的输出(第一个 u0441 u043b u043e u00a0上的神经元的输出(6、7、8、10、12、13。20、26,连接到输出的神经元的第二个 u0441 u043b u043e u00a0入口)第一个 u0441 u043b u043e u00a0上的神经元2、9、11、13、18、19、20、27个,连接到输出神经元的第二个神经元的入口3、3、10 、、 12、14、17、19、20、28,第一个 n044神经元,其中第二个 u0441 u043b u043e u00a0神经元连接到神经元的输出(4、7、9 ,12、15、19、20、29,第一个 u0441 u043b u043e u00a0神经元。第二个 u0441 u043b u043e u00a0入口 u0434 u0435 u0432 u00a0 u0442 u0 43e u0433 u043e神经元连接到第一个 u0441 u043b u043e 上神经元1、5、7、8、9、10、13、14、15、16、18、19、20、30的输出u00a0,入口 u0434 u0435 u0441 u00a0 u0442 u043e u0433 u043e神经元连接到神经元的第二个 u0441 u043b u043e u00a0输出(6、8、10、11、12、16、17 ,第一个 u0441 u043b u043e u00a0上的,18、20、31。

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