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PROTECTIVE schemes for self-protection electromagnetic actuators, as well as protective circuits for intrinsically safe power supply systems
PROTECTIVE schemes for self-protection electromagnetic actuators, as well as protective circuits for intrinsically safe power supply systems
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机译:自保护电磁执行器的保护方案,以及本质安全电源系统的保护电路
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1.u0437u0430u0449u0438u0442u043du0430u00a0 scheme u0434u043bu00a0 u0441u0430u043cu043eu0437u0430u0449u0438u0449u0435u043du043du044bu0445 electromagnetic u0430u043au0442u0443u0430u0442u043eu0440u043eu0432 activated u043du0430u043fu0440u00a0u0436u0435u043du0438u0435u043c block u043fu0438u0442u0430u043du0438u00a0 authorized u0434u043bu00a0 u0438u0441u043fu043eu043bu044cu0437u043eu0432u0430u043du0438u00a0 u0434u043bu00a0 underground guo u0440u043du044bu0445 works u0434u043bu00a0 u043fu0435u0440u0435u043au043bu044eu0447u0435u043du0438u00a0 u044du043bu0435u043au0442u0440u043eu0433u0438u0434u0440u0430u0432u043bu0438u0447u0435u0441u043au0438u0445 valve in underground mining work with at least u0434u0432u0443u043cu00a0 u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u044eu0449u0438u043cu0438 meansimplemented separately from each other and connected in parallel to a coil of an electromagnetic u0430u043au0442u0443u0430u0442u043eu0440u0430 u0434u043bu00a0 u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u043du0438u00a0 coils to change capabilities, e.g. u00a0u0436u0435u043du0438u00a0 u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0 coils so that at least one of the u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u044eu0449u0438u0445 means has u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u044eu0449u0438u0439 semiconductor switch (16, 16a) and u0434u0435u0442u0435u043au0442u043eu0440u043du0443u044e with u0445u0435u043cu0443 (30) u0434u043bu00a0 u0438u0437u043cu0435u043du0435u043du0438u00a0 capabilitieswith the help of which u0430u043au0442u0438u0432u0438u0440u0443u0435u0442u0441u00a0 u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u044eu0449u0438u0439 semiconductor switch (16, 16a).;2. u0437u0430u0449u0438u0442u043du0430u00a0 scheme on 1 u0438u0437u043eu0431u0440u0435u0442u0435u043du0438u00a0 u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0 formula, so that all u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u044eu0449u0438u0435 funds are u0434u0435u0442u0435u043au0442u043eu0440u043du0443u044e scheme with u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u044eu0449u0438u043c u043fu043eu043bu0443u043fu0440u043eu0432u043eu0434u043du0438u043au043eu0432u044bu043c u043fu0435u0440u0435u043au043bu044eu0447 u0430u0442u0435u043bu0435u043c.;3.u0437u0430u0449u0438u0442u043du0430u00a0 scheme u0434u043bu00a0 u0441u0430u043cu043eu0437u0430u0449u0438u0449u0435u043du043du044bu0445, underground systems u044du043du0435u0440u0433u043eu0441u043du0430u0431u0436u0435u043du0438u00a0 with several electronic devices u0443u043fu0440u0430u0432u043bu0435u043du0438u00a0, connected to a common cluster of u043fu0438u0442u0430u043du0438u00a0, u0440u0430u0437u0440 u0435u0448u0435u043du043du043eu043cu0443 u0434u043bu00a0 u0438u0441u043fu043eu043bu044cu0437u043eu0432u0430u043du0438u00a0 in underground mining work u0434u043bu00a0 u0430u043au0442u0438u0432u0438u0440u043eu0432u0430u043du0438u00a0 electromagnetic u0430u043au0442u0443u0430u0442u043eu0440u043eu0432,connected to the devices u0443u043fu0440u0430u0432u043bu0435u043du0438u00a0 and activated u043du0430u043fu0440u00a0u0436u0435u043du0438u0435u043c block u043fu0438u0442u0430u043du0438u00a0 u0434u043bu00a0 u043fu0435u0440u0435u043au043bu044eu0447u0435u043du0438u00a0 u044du043bu0435u043au0442u0440u043eu0433u0438u0434u0440u0430u0432u043bu0438u0447u0435u0441u043au0438u0445 valve in underground mining slave u043eu0442u0430u0445, each u044du043bu0435u043au0442u0440u043eu043cu0430u0433u043du0438u0442u043du043eu043cu0443 u0430u043au0442u0443u0430u0442u043eu0440u0443 attached to at least one u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u044eu0449u0435u0435 means in parallel to the coil u044du043bu0435u043au0442u0440u043eu043cu0430u0433u043du0438u0442u0430 u0434u043bu00a0 z u0430u043au043eu0440u0430u0447u0438u0432u0430u043du0438u00a0 coils to change the capacity of u043du0430u043fu0440u00a0u0436u0435u043du0438u00a0 coilsu043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0, u0437u0430u0449u0438u0442u043du0430u00a0 scheme (20; 40) has at least one u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u044eu0449u0435u0435 vehicle u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u044eu0449u0438u043c u043fu043eu043bu0443u043fu0440u043eu0432u043eu0434u043du0438u043au043eu0432u044bu043c switch (16, 16a) and u0434u0435u0442u0435u043au0442u043e u0440u043du043eu0439 pattern (30) u0434u043bu00a0 u0438u0437u043cu0435u043du0435u043du0438u00a0 capacities, through which u0430u043au0442u0438u0432u0438u0440u0443u0435u0442u0441u00a0 u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u044eu0449u0438u0439 semiconductor switch (16, 16a).;4. u0437u0430u0449u0438u0442u043du0430u00a0 scheme for 3 u0438u0437u043eu0431u0440u0435u0442u0435u043du0438u00a0 u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0 formula, so that at least one u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u044eu0449u0435u0435 vehicle u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u044eu0449u0438u043c u043fu043eu043bu0443u043fu0440u043eu0432u043eu0434u043du0438u043au043eu0432u044bu043c switch and detection scheme u00a0u0432u043bu00a0u0435u0442u0441u00a0 part of u0434u043eu043fu043eu043bu043du00a0u044eu0449u0435u0439 circuitry (40, 50), and u0434u043eu043fu043eu043bu043du00a0u044eu0449u0430u00a0 circuit preferably is located in u043fu0440u0435u0434u0432u043au043bu044eu0447u0435u043du043du043eu043c device (60).;5. u0437u0430u0449u0438u0442u043du0430u00a0 scheme for 3 or 4, u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0 so that each device u0443u043fu0440u0430u0432u043bu0435u043du0438u00a0 connected cluster u043fu0438u0442u0430u043du0438u00a0 (1) are attached to u0434u043eu043fu043eu043bu043du00a0u044eu0449u0430u00a0 circuitry (40, 50), in particular u043fu0440u0435u0434u0432u043au043bu044eu0447 u0435u043du043du044bu0439 device.;6. u0437u0430u0449u0438u0442u043du0430u00a0 scheme for 3, u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0 so that each electronic device (4) u0443u043fu0440u0430u0432u043bu0435u043du0438u00a0 given circuit (50) u043eu0433u0440u0430u043du0438u0447u0435u043du0438u00a0 current.;7. u0437u0430u0449u0438u0442u043du0430u00a0 scheme for p.6, u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0 what pattern (50) is u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u044eu0449u0438u0439 u043eu0433u0440u0430u043du0438u0447u0435u043du0438u00a0 dc semiconductor switch (56) and a reference pattern (51), u043au043eu0442u043eu0440u0430u00a0 act u0438u0432u0438u0440u0443u0435u0442 u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u044eu0449u0438u0439 semiconductor switch (56) to achieve a target amperage.;8. u0437u0430u0449u0438u0442u043du0430u00a0 scheme according to clause 5, u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0 what pattern (50) is an integral part of the u043eu0433u0440u0430u043du0438u0447u0435u043du0438u00a0 u00a0u0432u043bu00a0u0435u0442u0441u00a0 u043fu0440u0435u0434u0432u043au043bu044eu0447u0435u043du043du043eu0433u043e device (60).;9. u0437u0430u0449u0438u0442u043du0430u00a0 scheme for 1 or 3, u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0, u0434u0435u0442u0435u043au0442u043eu0440u043du0430u00a0 circuit (30) has an operational amplifier (31).;10. u0437u0430u0449u0438u0442u043du0430u00a0 scheme for u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0 p.9, so that u0434u0435u0442u0435u043au0442u043eu0440u043du0430u00a0 circuit including operational amplifier, implemented in the form of a comparator.;11. u0437u0430u0449u0438u0442u043du0430u00a0 scheme for u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0 p.9, so that the operational amplifier has u0438u043du0432u0435u0440u0442u0435u0440u043eu043c.;12. u0437u0430u0449u0438u0442u043du0430u00a0 scheme for 1 or 3, u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0, u0434u0435u0442u0435u043au0442u043eu0440u043du0430u00a0 circuit contains a transistor with an additional u043du0430u0433u0440u0443u0437u043eu0447u043du044bu043c resistor, which is connected to the front u0437u0430u043au043eu0440u0430u0447 u0438u0432u0430u044eu0449u0435u0433u043e semiconductor u043fu0435u0440u0435u043au043bu044eu0447u0430u0442u0435u043bu00a0.;13. u0437u0430u0449u0438u0442u043du0430u00a0 scheme for 1 or 3, u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0, u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u044eu0449u0438u0439 semiconductor switch consisting of a transistor.;14. u0437u0430u0449u0438u0442u043du0430u00a0 scheme on p.13, u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0, u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u044eu0449u0438u0439 semiconductor switch consists of a field transistor (16).;15. u0437u0430u0449u0438u0442u043du0430u00a0 scheme for 1 or 3, u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0, u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u044eu0449u0438u0439 semiconductor switch consists of u0442u0438u0440u0438u0441u0442u043eu0440u0430 (16a).;16. u0437u0430u0449u0438u0442u043du0430u00a0 scheme for 1 or 3, u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0 buffering storage (33), u0437u0430u0440u00a0u0436u0430u0435u043cu044bu043c because on a coil feed u043du0430u043fu0440u00a0u0436u0435u043du0438u00a0 block u043fu0438u0442u0430u043du0438u00a0 (1) as a separate u044du043du0435u0440u0433u043eu0441u043du0430u0431u0436u0435u043du0438u00a0 u0434u043bu00a0 detection circuitry (30).;17. u0437u0430u0449u0438u0442u043du0430u00a0 scheme on p.16, u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0, buffer storage (33) provides u043au043eu0440u043eu0442u043au043eu0437u0430u043cu043au043du0443u0442u043eu0435 u0441u043eu0441u0442u043eu00a0u043du0438u0435 u0437u0430u043au043eu0440u0430u0447u0438u0432u0430u044eu0449u0435u0433u043e semiconductor u043fu0435u0440u0435u043au043bu044eu0447u0430u0442u0435u043bu00a0 before the full u0440u0430u0437u0440u00a0u0434u0430 coils (11).;18. u0437u0430u0449u0438u0442u043du0430u00a0 scheme on p.16, u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0, buffer storage device contains a capacitor (33).
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