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Memory arrangement for processing and storing data, has address decoder connected with memory area and designed to identify memory cell assigning external addresses and non-addressed memory cell of sets
Memory arrangement for processing and storing data, has address decoder connected with memory area and designed to identify memory cell assigning external addresses and non-addressed memory cell of sets
The arrangement has an address decoder (2) connected with a memory area (1) having memory cells (100). The decoder is so switched that one of external addresses (EA) of an address area is assigned to each cell or only one of the addresses of partial address areas is assigned to each cell within the partial areas. The decoder is designed to identify the cell assigning the external addresses and non-addressed memory cell (101) of sets. An independent claim is also included for a method of operating a memory arrangement.
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