首页> 外国专利> Logic circuit for calculating result operand esp. for safety-sensitive applications, has two logic stages with first between input and intermediate node, and second between intermediate nodes and output

Logic circuit for calculating result operand esp. for safety-sensitive applications, has two logic stages with first between input and intermediate node, and second between intermediate nodes and output

机译:用于计算结果操作数esp的逻辑电路。对于安全敏感的应用程序,具有两个逻辑阶段,第一阶段在输入和中间节点之间,第二阶段在中间节点和输出之间

摘要

Logic circuit has first encoded input for receiving input operands (AM,BMN), second input for receiving second input operands (BM,BMN), and an encoding input for receiving the operands. First and second logic stages (101a,101b) are used, where the first (101a) is connected between inputs and an intermediate node (INT,INTN), and the second is connected between the intermediate nodes and output. The logic stages are designed according to logic specification with regard to encoding operands to calculate first- or second-logic state of the encoded result operands from the encoded input operands. An independent claim is included for a method for calculating an encoded dual-rail-result operand.
机译:逻辑电路具有用于接收输入操作数(AM,BMN)的第一编码输入,用于接收第二输入操作数(BM,BMN)的第二输入以及用于接收操作数的编码输入。使用第一和第二逻辑级(101a,101b),其中第一(101a)连接在输入和中间节点(INT,INTN)之间,第二逻辑级连接在中间节点和输出之间。根据关于编码操作数的逻辑规范来设计逻辑级,以从编码输入操作数计算编码结果操作数的第一或第二逻辑状态。为计算编码的双轨结果操作数的方法包括独立权利要求。

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