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Logic circuit for calculating result operand esp. for safety-sensitive applications, has two logic stages with first between input and intermediate node, and second between intermediate nodes and output
Logic circuit for calculating result operand esp. for safety-sensitive applications, has two logic stages with first between input and intermediate node, and second between intermediate nodes and output
Logic circuit has first encoded input for receiving input operands (AM,BMN), second input for receiving second input operands (BM,BMN), and an encoding input for receiving the operands. First and second logic stages (101a,101b) are used, where the first (101a) is connected between inputs and an intermediate node (INT,INTN), and the second is connected between the intermediate nodes and output. The logic stages are designed according to logic specification with regard to encoding operands to calculate first- or second-logic state of the encoded result operands from the encoded input operands. An independent claim is included for a method for calculating an encoded dual-rail-result operand.
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