Phase shifter for generating phase delayed output signal in synchronization device, has delay lines, one of which is connected to phase comparator while other delay line receives input signal for generating output signal

摘要

Each delay line (2,3) has cascaded delay components (4) that form a U-shaped signal path. A phase comparator (PD) receives an input clock pulse (CLKIN) and a signal from one of the delay lines. The phase comparator provides an output to the control inputs (DLCTR) of the delay components while the input clock pulse is also received by the delay line (2) such that a feedback loop is formed. An input signal (SIGIN) is input, not to the delay line whose signal output (OUT1,OUT2) is connected to the phase comparator, to produce an output signal (SIGOUT).