Content addressable memory cell, has memory circuit with comparison circuit having NMOS transistors and isolation transistors, which are implanted in respective active zones, where all transistors are oriented vertically

摘要

The cell has a memory circuit with NMOS and PMOS transistors (N1, N2, P1, P2) for the storage of data to be compared. Another memory circuit has NMOS and PMOS transistors (N3, N4, P3, P4) for the storage of validation or invalidation data, and a comparison circuit. The comparison circuit has NMOS transistors (N5-N7) and an isolation transistor (N11) that are implanted in an active zone (ZA4). The comparison circuit has NMOS transistors (N8-N10) and an isolation transistor (N12) that are implanted in an active zone (ZA5). All the transistors of the cell are oriented vertically. The gates of the transistors of the memory circuits and the gates of the transistors of the comparison circuit are put in communication by tracks.