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Method and apparatus for improving the throughput of a cache-based embedded processor by switching tasks in response to a cache miss
Method and apparatus for improving the throughput of a cache-based embedded processor by switching tasks in response to a cache miss
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机译:通过响应于高速缓存未命中而切换任务来提高基于高速缓存的嵌入式处理器的吞吐量的方法和装置
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摘要
A digital baseband processor is provided for concurrent operation with different wireless systems. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and a timing and event processor controlled by the digital signal processor and the microcontroller for executing timing-sensitive instructions. The timing and event processor includes a plurality of instruction sequencers for executing timing-sensitive instruction threads and a time base generator for generating timing signals for initiating execution of the instruction threads on each of the plurality of instruction sequencers.
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