首页> 外国专利> METHOD FOR REDUCING ELECTROMAGNETIC INTERFERENCE AND CLOCK MANAGEMENT CIRCUIT (COHERENT FREQUENCY CLOCK GENERATION AND SPECTRUM MANAGEMENT WITH NON-COHERENT PHASE)

METHOD FOR REDUCING ELECTROMAGNETIC INTERFERENCE AND CLOCK MANAGEMENT CIRCUIT (COHERENT FREQUENCY CLOCK GENERATION AND SPECTRUM MANAGEMENT WITH NON-COHERENT PHASE)

机译:减少电磁干扰和时钟管理电路的方法(非相干相干频率时钟产生和频谱管理)

摘要

PROBLEM TO BE SOLVED: To provide a method for reducing electromagnetic interference in a clocked circuit.;SOLUTION: In the disclosed method, the clock circuit includes at least a first clock signal and a second clock signal. The method detects when a first transition of the first clock signal is substantially aligned with a corresponding second transition of the second clock signal. The method further delays the second clock signal by a predetermined amount of time when the first transition is substantially aligned with the second transition.;COPYRIGHT: (C)2008,JPO&INPIT
机译:解决的问题:提供一种减少时钟电路中的电磁干扰的方法。解决方案:在所公开的方法中,时钟电路至少包括第一时钟信号和第二时钟信号。该方法检测第一时钟信号的第一转变与第二时钟信号的相应第二转变何时基本对准。当第一过渡基本上与第二过渡对齐时,该方法还将第二时钟信号延迟预定的时间量。版权所有:(C)2008,JPO&INPIT

著录项

  • 公开/公告号JP2008005503A

    专利类型

  • 公开/公告日2008-01-10

    原文格式PDF

  • 申请/专利权人 INTERNATL BUSINESS MACH CORP IBM;

    申请/专利号JP20070163374

  • 发明设计人 GILLILAND DON A;

    申请日2007-06-21

  • 分类号H03K5/1252;H03K5/19;H03K5/12;G06F1/10;

  • 国家 JP

  • 入库时间 2022-08-21 20:18:37

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