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Circuit parameter extraction method, the design method and apparatus for a semiconductor integrated circuit

机译:半导体集成电路的电路参数提取方法,设计方法和装置

摘要

PROBLEM TO BE SOLVED: To enable highly precise calculation of finished wiring width and highly precise circuit simulation. SOLUTION: Correlation data 101 between the distance between model wiring and wiring existing around the model wiring in the same layer and the difference between the mask-layout width and the finished width of the model wiring are prepared, the wiring length and wiring width of analyzing wiring and the distance between the analyzing wiring and the wiring existing around the analyzing wiring in the same layer are extracted from the actual layout 100 (102), and wiring resistance value and wiring capacitance value with respect to the extracted layout-wiring width of the analyzing wiring and the extracted distance between the analyzing wiring and the wiring existing around the analyzing wiring are calculated by using finished wiring width obtained by referring to the correlation data (105).
机译:要解决的问题:能够高精度地计算出完成的布线宽度并进行高精度的电路仿真。解决方案:准备模型布线之间的距离与同一层模型布线周围存在的布线之间的距离以及掩膜版图宽度与模型布线完成宽度之间的差值的相关数据101,并分析布线长度和布线宽度从实际布局100中提取布线以及分析布线与存在于同一层中的分析布线周围的布线之间的距离(102),并且相对于所提取的布线宽度,布线电阻值和布线电容值。通过使用参考相关数据获得的最终布线宽度来计算分析布线和在分析布线与存在于分析布线周围的布线之间的提取距离(105)。

著录项

  • 公开/公告号JP4018309B2

    专利类型

  • 公开/公告日2007-12-05

    原文格式PDF

  • 申请/专利权人 松下電器産業株式会社;

    申请/专利号JP20000035267

  • 发明设计人 石倉 聡;

    申请日2000-02-14

  • 分类号H01L21/82;G03F1/08;G06F17/50;H01L21/027;

  • 国家 JP

  • 入库时间 2022-08-21 20:16:57

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