首页>
外国专利>
LATCHING INPUT BUFFER CIRCUIT WITH VARIABLE HYSTERESIS
LATCHING INPUT BUFFER CIRCUIT WITH VARIABLE HYSTERESIS
展开▼
机译:锁存可变迟滞的输入缓冲电路
展开▼
页面导航
摘要
著录项
相似文献
摘要
An input buffer circuit with hysteresis includes a first stage and a second stage. The first stage includes a resistive device to provide a resistance between two nodes of the first stage. The two nodes are responsive to a signal input. The second stage includes four series-coupled transistors. A first node is coupled to the control electrodes of two of the four transistors and the second node is coupled to the control electrodes of the other two transistors. The second stage includes a signal output. In some examples, a resistance provided by the resistive device is variable and provides the buffer circuit with hysteresis.
展开▼