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Register File Bypass With Optional Results Storage and Separate Predication Register File in a VLIW Processor
Register File Bypass With Optional Results Storage and Separate Predication Register File in a VLIW Processor
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机译:在VLIW处理器中注册带有可选结果的文件旁路和单独的谓词注册文件
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摘要
This invention makes each register bypass forwarding register explicitly addressable in software. Software chooses whether to access the forwarding register immediately eliminating the need for complex automatic detection. Each instruction executes and always writes its result into the forwarding register. Writing this data into the register file in the next cycle is optional as selected by the destination register file number. This invention separates registers storing predication data from the register file. This separation removes the speed problem by enabling scheduling of the predication computation out of the critical path.
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