METHOD, COMPUTER PROGRAM PRODUCT, AND TOOL FOR TIMING PERFORMANCE OF A HIERARCHICAL CHIP DESIGN HAVING MULTIPLE PARTITION INSTANCES

摘要

Timing resources are saved in timing performance of a hiearchial chip design having multiple partition instances. A netlist of the chip design is loaded into a timing model, including only one instance of each partition type in the chip design. The timing model is instructed to ignore boundary timing. The timing model is run, analyzing only the internal paths of one instance of each partition type. The top level of the chip design is also loaded into the timing model and left intact. The timing model also takes into account actual voltage and parasitic information from the full chip model. Thus, the performance of the chip design can be timed faster and with fewer resources, as each instance of each partition type does not need to be timed.