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Design verification of highly optimized synchronous pipelines via random simulation driven by critical resource scheduling
Design verification of highly optimized synchronous pipelines via random simulation driven by critical resource scheduling
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机译:通过关键资源调度驱动的随机模拟对高度优化的同步管道进行设计验证
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摘要
Testing a model of a logic circuit model. The testing includes generating valid random input stimulus sequences for a logic circuit model. Enumerating critical resource requirements, enumerating critical resource availabilities does this, and selecting of stimulus sequences and determining legal times for execution of said stimulus sequences based on resource availability. This includes generating a plurality of possible combinations of input stimulus sequences and generating an array representation of critical resource requirements. These are used to generate an array representation of critical resources availabilities.
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