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Integration of strained Ge into advanced CMOS technology
Integration of strained Ge into advanced CMOS technology
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机译:将应变Ge集成到先进的CMOS技术中
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摘要
A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.
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