Hybrid high-speed/low-speed output latch in 10 GBPS interface with half rate clock

摘要

A high-speed serial demultiplexer receives over four high-speed serial data lines at a nominal rate of 10 GBPS and demultiplexes the data to 16 lines with a rate of 2.5 GHz each. The demultiplexer circuits are configured as two D type latches, one of which latches data on the positive edge of a 5 GHz clock, the other of which latches every other bit of the 10 GBPS data on the negative edge of the 5 GHz clock, alternating with the first D latch. Each of the two D latches is configured as a master-slave flip-flop that includes a master D latch and a slave D latch. The master receives the data at the 10 GBPS rate and clocks every other bit to its output using an edge of the 5 GHz clock (the positive edge for one of the D-latches, the negative for the other). The slave clocks the data form the master to its output on the opposite edge of the clock following the master.