首页> 外国专利> Frequency divider circuit with controllable frequency division ratio and method for frequency division in a frequency divider circuit

Frequency divider circuit with controllable frequency division ratio and method for frequency division in a frequency divider circuit

机译:分频比可控的分频器电路及分频器电路中的分频方法

摘要

A frequency divider circuit is disclosed with at least one push-pull divider with adjustable division ratio and a connected converter device. The circuit converts a clock signal delivered by a push-pull divider into a single-ended signal. A first and a second single-ended divider are connected to the output of the converter device, and a feedback path is provided, which is connected to the output of the push-pull divider and to the outputs of the first and of the at least one second single-ended divider, and which includes an evaluation circuit. This circuit has first and second inputs which are connected to the first and second single-ended dividers in such a way that a future state of the clock signal delivered by the single-ended divider in question can be supplied to the inputs of the evaluation circuit. The evaluation circuit evaluates states of the clock signals delivered by the first and second single-ended dividers, i.e., states which will not exist until after future switching functions have been performed. As a result, additional time is gained for converting the signal to be divided from a push-pull signal to a single-ended signal.
机译:公开了一种分频器电路,其具有至少一个具有可调分频比的推挽分频器和连接的转换器装置。该电路将推挽分频器提供的时钟信号转换为单端信号。第一和第二单端除法器连接到转换器设备的输出,并提供反馈路径,该反馈路径连接到推挽式除法器的输出以及第一和至少一个的输出。一个第二单端分频器,它包括一个评估电路。该电路具有第一和第二输入端,它们以这种方式连接到第一和第二单端分频器,使得可以将所讨论的单端分频器传送的时钟信号的未来状态提供给评估电路的输入。 。评估电路评估由第一和第二单端分频器传送的时钟信号的状态,即直到执行了将来的切换功能之后才存在的状态。结果,获得了额外的时间来将要划分的信号从推挽信号转换为单端信号。

著录项

  • 公开/公告号US7298184B2

    专利类型

  • 公开/公告日2007-11-20

    原文格式PDF

  • 申请/专利权人 JÖRN ANGEL;

    申请/专利号US20060513655

  • 发明设计人 JÖRN ANGEL;

    申请日2006-08-31

  • 分类号H03K23;

  • 国家 US

  • 入库时间 2022-08-21 20:09:48

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