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Disconnection and short detecting circuit that can detect disconnection and short of a signal line transmitting a differential clock signal
Disconnection and short detecting circuit that can detect disconnection and short of a signal line transmitting a differential clock signal
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机译:断线和短路检测电路,可以检测传输差分时钟信号的信号线的断线和短路
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摘要
Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted from a PADI and an inverting clock signal inputted from a PADR; a second comparator to compare a non-inverting clock signal and a reference potential Vref; and a third comparator to compare an inverting clock signal and the reference potential Vref. Their respective outputs are defined as Y, YI and YR, respectively. If the signal line of either a non-inverting clock signal or an inverting clock signal is disconnected, or short-circuited to a grounding potential VSS of a logical value Low, the logical values outputted from the second and the third comparators are equal for a long period of time in one cycle of the non-inverting clock signal or the inverting clock signal. Thereby, if a second D-flip-flop circuit F2a negates an output signal [CD], it is able to judge that disconnection or short occurs.
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机译:提供了一种断开和短路检测电路,其能够检测发送差分时钟信号的信号线的断开和短路。差分缓冲器部分DB 1 B>具有第一比较器,用于比较从PADI输入的同相时钟信号和从PADR输入的同相时钟信号。第二比较器比较同相时钟信号和参考电位Vref;第三比较器比较反相时钟信号和参考电位Vref。它们各自的输出分别定义为Y,YI和YR。如果同相时钟信号或反相时钟信号的信号线断开或短路到逻辑电位为低的接地电位VSS,则从第二比较器和第三比较器输出的逻辑值等于在同相时钟信号或反相时钟信号的一个周期中较长的时间。从而,如果第二D触发器电路F 2 B> a I>使输出信号[CD]取反,则能够判断发生断开或短路。
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