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Method and system for formal unidirectional bus verification using synthesizing constrained drivers
Method and system for formal unidirectional bus verification using synthesizing constrained drivers
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机译:使用综合约束驱动器进行形式化单向总线验证的方法和系统
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摘要
A method, system and computer program product for performing verification is disclosed. A high-level description of a design is created and constrained drivers are synthesized from the high-level description of the design. A testbench is generated from the high-level description of the design and the constrained drivers and a formal equivalence is evaluated on the testbench to perform verification.
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