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FRACTIONAL-WORD WRITABLE ARCHITECTED REGISTER FOR DIRECT ACCUMULATION OF MISALIGNED DATA
FRACTIONAL-WORD WRITABLE ARCHITECTED REGISTER FOR DIRECT ACCUMULATION OF MISALIGNED DATA
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机译:直接累积错误数据的分数维可写结构化寄存器
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摘要
One or more architected registers in a processor are fractional-word writable, and data from plural misaligned memory access operations are assembled directly in an architected register, without first assembling the data in a fractional-word writable, non-architected register and then transferring it to the architected register. In embodiments where a general-purpose register file utilizes register renaming or a reorder buffer, data from plural misaligned memory access operations are assembled directly in a fractional-word writable architected register, without the need to fully exception check both misaligned memory access operations before performing the first memory access operation.
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