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Design of channel alignment, error handling, and clock routing using hard-wired blocks for data transmission within programmable logic integrated circuits
Design of channel alignment, error handling, and clock routing using hard-wired blocks for data transmission within programmable logic integrated circuits
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机译:使用硬连线模块设计通道对齐,错误处理和时钟路由,以在可编程逻辑集成电路内进行数据传输
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摘要
Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.
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