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METHOD OF INTERFACING GPS MODULE AND CPU NOT SUPPORTING PARITY BIT
METHOD OF INTERFACING GPS MODULE AND CPU NOT SUPPORTING PARITY BIT
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机译:接口GPS模块和CPU不支持奇偶校验位的方法
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摘要
It is a kind of for method without support engagement one GPS (GPS) module and a CPU (central processing unit) parity check bits be arranged to reduce for a navigation equipment a cost and improve receptivity engagement GPS and CPU. It is a kind of for method without support engagement one GPS module (11) and (15) one parity check bits of a CPU, comprising the following steps: foundation passes through the communication of CPU; It includes prior knowledge to GPS module that data for the first time are transmitted before an enabling signal by the equivalent processes logic (20) in CPU; Increase a parity check bit to pass through equivalent processes logic input data for the first time inside and transmit for the first time data to GPS module; Receiving data for the first time and the second data of transmission by equivalent processes logic includes current location information to CPU; Parity check bit is removed from the second data and transmits the second data to CPU.
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