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METHOD OF INTERFACING GPS MODULE AND CPU NOT SUPPORTING PARITY BIT

机译:接口GPS模块和CPU不支持奇偶校验位的方法

摘要

It is a kind of for method without support engagement one GPS (GPS) module and a CPU (central processing unit) parity check bits be arranged to reduce for a navigation equipment a cost and improve receptivity engagement GPS and CPU. It is a kind of for method without support engagement one GPS module (11) and (15) one parity check bits of a CPU, comprising the following steps: foundation passes through the communication of CPU; It includes prior knowledge to GPS module that data for the first time are transmitted before an enabling signal by the equivalent processes logic (20) in CPU; Increase a parity check bit to pass through equivalent processes logic input data for the first time inside and transmit for the first time data to GPS module; Receiving data for the first time and the second data of transmission by equivalent processes logic includes current location information to CPU; Parity check bit is removed from the second data and transmits the second data to CPU.
机译:这是一种不支持接合的GPS方法,其中一个GPS(GPS)模块和一个CPU(中央处理单元)奇偶校验位被安排来减少导航设备的成本并提高GPS和CPU的接收接合性。这是一种不支持参与的方法,其中一个GPS模块(11)和(15)一个CPU的奇偶校验位,包括以下步骤:基础通过CPU的通信;它包括GPS模块的先验知识,即首次数据是在CPU中的等效处理逻辑(20)在启用信号之前发送的;首次增加一个奇偶校验位通过等效处理逻辑输入数据,并首次将数据传输到GPS模块;通过等效处理逻辑第一次接收数据和第二次发送数据包括到CPU的当前位置信息;奇偶校验位从第二数据中删除,并将第二数据发送到CPU。

著录项

  • 公开/公告号KR20070109228A

    专利类型

  • 公开/公告日2007-11-15

    原文格式PDF

  • 申请/专利权人 MOBIDIC. CO. LTD.;

    申请/专利号KR20060041925

  • 发明设计人 YOON JUNG HWAN;KIM HYUN TAE;

    申请日2006-05-10

  • 分类号G06F13/14;

  • 国家 KR

  • 入库时间 2022-08-21 19:54:53

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