METHOD FOR CHANGING PHYSICAL LAYOUT DATA BY USING VIRTUAL LAYER

摘要

A method for changing physical layout data by generating a physical layer via programs is provided to enable reliable physical test by using an LVS(Logic Versus Schematic)/DRC(Design Rule Check) appropriate for fabrication in which a real process is proceeded. A method for changing physical layout data by generating a physical layer via programs comprises the following several steps. Coating for a target design is performed and logics are integrated(S310). A virtual layer is generated by using the cadence SKILL program(S320). Each logic block is placed at a corresponding position and place & routing is performed for connecting the logic block to an executing element(S330). LPE(Layout Parasitic Extraction) is performed for extracting definitely a routing register capacitance value from a layout which has finished the place & routing for the integration of the logics, and a timing is checked and crosstalk is analyzed by using STA(Static Timing Analysis) for physical implementation(S340). LVS is performed for checking whether interconnection or routing of transistors is matched with a circuit, and a DRC is performed for checking whether a routing space and a gate length conform to preset specifications(S350). A mask is produced by using OPC(Optical Proximity Correction) on the basis of the generated virtual layer(S360).