SEMICONDUCTOR IC INCLUDING PAD FOR WAFER TEST AND TEST METHOD FOR WAFER INCLUDING SEMICONDUCTOR IC

摘要

Semiconductor integrated circuit include disclose including pad be used for wafer test and semiconductor integrated circuit chip testing method. It generates a first address and includes that semiconductor integrated circuit divides according to one embodiment of present invention, including one second address generating set and an address output. It generates a normal address or M of the address for detecting N+M for the first time corresponding with the voltage of first address generating set is applied to and enters multiple address pads. The place of related pad generates a second test of N- bit address corresponding with the voltage of the second address generating set is applied to. The testing method of one chip includes semiconductor integrated circuit and semiconductor integrated circuit pass through according to the present invention reduce quantity pad that should to be connected to testing equipment include a test pad, it is used to generate the address from the positions N of wafer test mode, while having the advantage that the quantity for the semiconductor integrated circuit that increase can be tested.