A parallel processing processor architecture adapting adaptive pipeline is provided to remove unnecessary operation from a system and process various kinds of instructions in parallel without increasing hardware by applying asynchronous adaptive pipeline and a parallel processing mode to the system. Each pipeline stage latch/controller selects storage of data depending on a control signal to store input depending on a data path requested from an executed instruction or to transfer the data to a next stage. Each pipeline stage selectively transfers the data to the next stage latch/controller after operation or without any operation depending on the requested data path. An IF stage(121) discriminates whether the received instruction is an ARM(Advanced RISC(Reduced Instruction Set Computer) Machines) or thumb instruction by performing pre-decoding. An ID stage comprises a second stage(130a) including a thumb decoder(D1), a third stage(130b) including an ARM decoder(D2), and a third stage(130c) including a decoder(D3) discriminatingly outputting the decoded thumb or ARM instruction. A sixth stage(140b) executes the operation according to the instruction by receiving the decoded instructions at the same time.
展开▼
