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PLL with short period of stabilizing and Method for stabilizing the frequency and phase with short period
PLL with short period of stabilizing and Method for stabilizing the frequency and phase with short period
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机译:短周期稳定的PLL及短周期稳定频率和相位的方法
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摘要
A PLL(Phase Locked Loop) having a short stabilizing period and a method for stabilizing a frequency and a phase having a short stabilizing period are provided to obtain a fast stabilizing time by adjusting the number of frequency multiplication without a stabilizing problem. A frequency detector(110) generates a frequency comparison signal in response to a reference signal and a control voltage. An FSM(Finite State Machine)(120) generates a frequency locked signal, an oscillation control signal, a first frequency control signal, a second frequency control signal in response to the reference clock signal and the frequency comparison signal. A phase detector(130) generates a first phase control signal and a second phase control signal by comparing a phase of the reference clock signal with a phase of an internal clock signal in response to the frequency locked signal. A logic circuit(140) generates first and second charge pump control signals in response to the first and second frequency control signals and first and second phase control signals. A charge pump generates a control voltage in response to the first and second charge pump control signals. A loop filter filters the control voltage. A voltage controlled oscillator(180) generates an oscillation signal in response to the oscillation controlled signal and the control voltage. A divider generates the internal clock signal by dividing a frequency of the oscillated signal.
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