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METHOD OF PAYMENT OF INTERNAL DELAYS WITHIN each node and transmission delays between nodes

机译:每个节点内部延迟的支付方法以及节点之间的传输延迟

摘要

1.method u0434u043bu00a0 synchronization of real time the first node and the second node hours of real time, real time clock u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 containing phases. which u043eu0442u043fu0440u0430u0432u043bu00a0u044eu0442 real time clock u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 and number one on the first node, the first node set real time clock.equal hours of real time u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430; forming the second number; u043eu0442u043fu0440u0430u0432u043bu00a0u044eu0442 real time clock u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 and the second number to the second node and imposed real time clock to the second node, u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 equal hours of real time.;2. method for 1, further containing phase to establish the network address of the first node u0434u043bu00a0, equal to the first number.;3. a way to 2, in which the network address of the first node u0434u043bu00a0, equal to the first number, u0432u044bu043fu043eu043bu043du00a0u0435u0442u0441u00a0 first node.;4. method for 1, in which the hours of real time u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 rooms on the first node and the first u0432u044bu043fu043eu043bu043du00a0u0435u0442u0441u00a0 u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u043eu043c.;5. method for 1, in which the hours of real time clock real time equal to the first node, the first node in the u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430, u0432u044bu043fu043eu043bu043du00a0u0435u0442u0441u00a0.;6. method for 1, in which the formation of the second non u0432u044bu043fu043eu043bu043du00a0u0435u0442u0441u00a0 first node.;7. method for 1, in which the hours of real time u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 and number two at the second node of the first node in the u0432u044bu043fu043eu043bu043du00a0u0435u0442u0441u00a0.;8. method for 1, in which the hours of real time clock real time equal to the second node, the second node u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430, u0432u044bu043fu043eu043bu043du00a0u0435u0442u0441u00a0.;9. method for 1, in which the hours of real time u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 and first non contains stages in which form the u0441u0438u043du0445u0440u043eu0441u043bu043eu0432u043e containing real clock wow time u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 and first number; and u043eu0442u043fu0440u0430u0432u043bu00a0u044eu0442 u0441u0438u043du0445u0440u043eu0441u043bu043eu0432u043e at the first node.;10. method for p.9, in which the hours of real time u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 and number two at the second node contains stages in which modify the u0441u0438u043du0445u0440u043eu0441u043bu043eu0432u043e u043fu043eu0441u0440u0435 u0434u0441u0442u0432u043eu043c u0437u0430u043cu0435u0449u0435u043du0438u00a0 first non number two; and u043eu0442u043fu0440u0430u0432u043bu00a0u044eu0442 modified u0441u0438u043du0445u0440u043eu0441u043bu043eu0432u043e at the second node.;11. method for 1, in which the first node, the second node and the multiplexer are connected to each other in u0448u043bu0435u0439u0444u043eu0432u043eu0439 configuration.;12. method for u043fu0435u0440u0435u0434u0430u044eu0442u0441u00a0 1, in which the data between the first node and the second node and u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u043eu043c using u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u0438u0440u043eu0432u0430u043du0438u00a0 with temporal separation (tdm).;13. method for 1, further containing phase to establish the network address of the second node u0434u043bu00a0, equal to the second number.;14. method for 1, in which the second plate includes a step in which the first u043eu0441u0443u0449u0435u0441u0442u0432u043bu00a0u044eu0442 increment numbers on the unit.;15.method u0434u043bu00a0 compensation of one or more delay transfer between u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u043eu043c, the first node and the second node containing the stages in which counting delay p u0435u0440u0435u0434u0430u0447u0438 between u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u043eu043c and the first node using the u0443u0440u0430u0432u043du0435u043du0438u00a0 (RTCu043a + Delayu043a) mod (MTslot) = (k - 1) Tslot, where m denotes the number of time intervals within the strips s u043fu0440u043eu043fu0443u0441u043au0430u043du0438u00a0 environmentu0441u043au043eu043du0444u0438u0433u0443u0440u0438u0440u043eu0432u0430u043du043du043eu0439 u0434u043bu00a0 transfer of data between the first node and the second node u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u043eu043c, denotes the length of each time interval, Tslot, k denotes the address of the host u0432u0437u00a0u0442u0438u00a0 mod denotes the operation module, RTCu043a stands for real time clock k th node, and Delayu043a denotes the accumulated delay transmission of u043cu0443u043bu044cu0442u0438u043fu043bu0435u043a look at the k th node; u043eu0442u043fu0440u0430u0432u043bu00a0u044eu0442 real time clock u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430,the first number and the delay of the first node; and establishing a real time clock first node equal hours of real time u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430, plus u0437u0430u0434u0435u0440u0436 this transfer.;16. method for p.15, additionally containing a phase in which the u043eu0442u043fu0440u0430u0432u043bu00a0u044eu0442 data multiplexer used in u0432u0440u0435u043cu00a0, a delay of transmission.;17. method for p.15, additionally containing a phase in which the expected delay between the first node and the second node transmission using u0443u0440u0430u0432u043du0435u043du0438u00a0.;18. way to p.17, further containing stages in which u043eu0441u0443u0449u0435u0441u0442u0432u043bu00a0u044eu0442 increment of numbers on the unit to form a second number; and u043eu0442u043fu0440u0430u0432u043bu00a0u044eu0442 on u0432u0442u043eu0440 oh, the real time clock u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430, number 2, the delay of transfer between u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u043eu043c and the first node, and the delay between the first node and u0432u0442u043eu0440 transfer ies knot.;19. way on p.18, additionally containing a phase in which the set real time clock real time clock for the second node, the same u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430, plus three u0430u0434u0435u0440u0436u043au0430 transfer between u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u043eu043c and the first node, plus the delay transmission between the first node and the second node.;20. way on p.19, additionally containing a phase in which the u043eu0442u043fu0440u0430u0432u043bu00a0u044eu0442 data multiplexer used in u0432u0440u0435u043cu00a0, a delay of transfer between u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u043e m and the first node, plus the delay between the first node and the second node transmission.;21. method for p.15, which contains the transmission delay caused by the internal processing of data within the first node.;22. method for calculating delay, p.15, in which transmission between u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u043eu043c and the first node includes a stage in which the difference between the time data and u043fu0440u0438u0431u044bu0442u0438u00a0 u0438u0437u043cu0435u0440u00a0u044eu0442 the first node in the multiplexer and the time u043fu0440u0438u0431u044bu0442u0438u00a0, calculated using the u0443u0440u0430u0432u043du0435u043du0438u00a0.;23. method for calculating delay, p.22, in which transmission between the first node u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u043eu043c and further contains a phase in which the expected delay of transfer between do u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u043eu043c and the first node using the measured difference.;24. method for p.15, further containing phase to establish the network address of the first node u0434u043bu00a0, equal to the first number.;25. method for calculating delay, p.17, in which transmission between the first node and the second node includes a stage in which the difference between the time u0438u0437u043cu0435u0440u00a0u044eu0442 u043fu0440u0438u0431u044bu0442u0438u00a0 data from bw u043eu0440u043eu0433u043e node at the first node and the time u043fu0440u0438u0431u044bu0442u0438u00a0, calculated using the u0443u0440u0430u0432u043du0435u043du0438u00a0.;26. way on p.25, in which the calculation delay transfer between the first node and the second node further includes a stage in which the expected delay transfer between p u0435u0440u0432u044bu043c node and the second node using the measured difference.;27.method u0434u043bu00a0 compensation of one or more delay transfer between u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u043eu043c, the first node and the second node containing phases.to synchronize the first real time clock u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 as hours of real time of first node, and as the hours of real time u0432u0442u043eu0440 wow node; taking data from a first node; counting the delay between the first node and the transmission u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u043eu043c using u0443u0440u0430u0432u043du0435u043du0438u00a0 (RTCu043a + Delayu043a) mod (MTslot) = (k - 1) Tslot,where m denotes the number of time intervals within the u043fu0440u043eu043fu0443u0441u043au0430u043du0438u00a0 environment, u0441u043au043eu043du0444u0438u0433u0443u0440u0438u0440u043eu0432u0430u043du043du043eu0439 u0434u043bu00a0 transfer of data between the first node u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u043eu043c, and the second node, Tslot denotes the length of each time interval, k denotes the address of the host u0432u0437u00a0u0442u0438u00a0 mod denotes the operation module, RTCu043a refers to watch real madrid u044cu043du043eu0433u043e time k th nodeand Delayu043a denotes the accumulated delay transmission of u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 at the k th node; u043eu0442u043fu0440u0430u0432u043bu00a0u044eu0442 second real time clock u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430, the first number and the delay tap u0440u0435u0434u0430u0447u0438 at the first node; and establishing a real time clock first node equal to the second clock real time u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430, plus the delay of transmission.;28. way on p.27, additionally containing a phase in which the u043eu0442u043fu0440u0430u0432u043bu00a0u044eu0442 data multiplexer used in u0432u0440u0435u043cu00a0, a delay of transmission.;29. method for p.27, which synchronize the first real time clock real time clock u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 as the first node and the second node of the real time clock. u0436u0430u0449u0438u0439 stageswhich u043eu0442u043fu0440u0430u0432u043bu00a0u044eu0442 first real time clock u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 and number one on the first node, the first node in the set real time clock as the first hours of real time u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430; forming the second number; u043eu0442u043fu0440u0430u0432u043bu00a0u044eu0442 first real time clock u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 and number two at the second node; and imposed real time clock to the second node.as the first, real time u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430.
机译:1.方法 u0434 u043b u00a0实时同步第一节点和第二节点的实时小时数,实时时钟 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430包含阶段。其中 u043e u0442 u043f u0440 u0430 u0432 u043b u00a0 u044e u0442实时时钟 u043c u0443 u043b u044c u0442 u0438 u043f u043f u043b u0435 u043a u0441 u043e u043e u0440 u0430和第一个节点上的第一个节点,第一个节点设置了实时时钟。等时的实时时间 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430;形成第二个数字; u043e u0442 u043f u0440 u0430 u0432 u043b u00a0 u044e u044e u0442实时时钟 u043c u0443 u043b u044c u0442 u0438 u043f u043b u043b u0435 u043a u0441 u043e u043e u0440 u0430和第二个数字分配给第二个节点,并向第二个节点施加实时时钟 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430实时; 2。 1的方​​法,进一步包含建立第一节点的网络地址等于第一数字的阶段。通往2的方式,其中第一个节点 u0434 u043b u00a0的网络地址等于第一个数字 u0432 u044b u043f u043e u043b u043d u00a0 u0435 u0442 u0441 u00a0首先节点; 4。 1的方​​法,其中第一个节点和第一个 u0432上的实时客房 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430 u044b u043f u043e u043b u043d u00a0 u0435 u0442 u0441 u0040c ; 5。 1的方​​法,其中实时时钟的实时时间等于第一个节点的时间,即 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430, u0432 u044b u043f u043e u043b u043d u00a0 u0435 u0442 u0441 u00a0。; 6。 1的方​​法,其中形成第二个非第一个非结点。7 .. 1的方​​法,其中实时时间 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430和第一个节点的第二个节点上的第二个在 u0432 u044b u043f u043e u043b u043d u00a0 u0435 u0442 u0441 u00a0中; 8。 1的方​​法,其中实时时钟的小时数等于第二个节点的时间,第二个节点 u043c u0443 u043b u043c u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430, u0432 u044b u043f u043e u043b u043d u00a0 u0435 u0442 u0441 u00a0。; 9。 1的方​​法,其中实时时间 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430和第一个非包含组成 u0441的阶段 u0438 u043d u0445 u0440 u043e u0441 u043b u043e u0432 u043e包含真实的时钟哇时间 u043c u0443 u043b u044c u0442 u0438 u043f u043b u043b u0435 u043a u0441 u043e u043e u0440 u0430和第一个数字;和 u043e u0442 u043f u0440 u0430 u0432 u043b u00a0 u044e u0442 u0441 u0438 u043d u0445 u0440 u043e u0441 u043b u043b u043e u0432 u043e 。第9页的方法,其中实时时间 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430和第二个节点的第二个小时数包含阶段在其中修改 u0441 u0438 u043d u0445 u0440 u043e u0441 u043b u043e u0432 u043e u043f u043e u0441 u0440 u0435 u0434 u0441 u0441 u0442 u0432 u043e u043c u043c u0430 u043c u0435 u0449 u0435 u043d u0438 u00a0第一个非第二数字; ;和 u043e u0442 u043f u0440 u0430 u0432 u043b u00a0 u044e u0442修改的 u0441 u0438 u043d u0445 u0440 u04340 u043e u0441 u0431 u043b u043e u043e u0432 u043e 11。 1的方​​法,其中第一节点,第二节点和多路复用器以 u0448 u043b u0435 u0439 u0444 u043e u0432 u043e u0439的配置相互连接; 12。 u043f u0435 u0440 u0435 u0434 u0430 u044e u0442 u0441 u00a0 1的方法,其中第一个节点和第二个节点之间的数据与 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u043e u043c使用 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u043a u0441 u0438 u0440 u043e u0432 u043d u0438 u00a0,具有时间间隔(tdm)。;13。 1的方​​法,进一步包含建立第二节点的网络地址的阶段,等于第二个数字。 1的方​​法,其中第二个板包括一个步骤,其中第一个 u043e u0441 u0443 u0449 u0435 u0441 u0442 u0432 u043b u00a0 u044e u0442在设备上递增编号。15。方法 u0434 u043b u00a0补偿 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u043e u043c之间的一个或多个延迟传输,第一个节点和第二个节点包含其中计数延迟p u0435 u0440 u0435 u0434 u0430 u0447 u0438之间的阶段,其中 u043c u0443 u043b u044c u0442 u0438 u043f u043b u043b u0435 u043a u0441 u043e u0440 u043e u043c,第一个节点使用 u0443 u0440 u0430 u0432 u043d u0435 u043d u0438 u00a0(RTC u043a + Delay u043a)mod(MTslot)=( k-1)Tslot,其中m表示条带s中的时间间隔数 u043f u0440 u043e u043f u0443 u0441 u043a u0430 u043d u0438 u00a0环境 u0441 u043a u043e u043d u0444 u0438 u0433 u0443 u0440 u0438 u0440 u043e u0432 u0430 u043d u043d u043e u0439 u0434 u043b u00a0第一节点和第二节点之间的数据传输 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u043e u043c,表示每个时间间隔的长度,Tslot,k表示主机的地址 u0432 u0437 u00a0 u0442 u0438 u00a0 mod表示操作模块,RTC u043a代表第k个实时时钟节点,Dela y u043a表示在第k个节点上的 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a的累积延迟传输; u043e u0442 u043f u0440 u0430 u0432 u043b u00a0 u044e u044e u0442实时时钟 u043c u0443 u043b u044c u0442 u0438 u043f u043b u043b u0435 u043a u0441 u043e u043e u0440 u0430,第一个节点的编号和延迟;并建立一个等于实时小时数的实时时钟第一个节点 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430,再加上 u0437 u0430 u0434 u0435 u0440 u0436此转移。; 16。第15页的方法,另外包含一个阶段,其中 u0432 u0440 u0435 u0435 u043c u00a0中使用的数据复用器 u043e u0442 u043f u0440 u0430 u0432 u043b u00a0传播; 17。第15页的方法,还包含一个阶段,其中使用 u0443 u0440 u0430 u0432 u043d u0435 u043d u0438 u00a0。; 18,在第一节点和第二节点之间传输预期的延迟。进入第17页的方式,进一步包含以下步骤:在单元上增加数字,以使第二个数字递增;第二个数字在单元中递增;第二个数字在单元中递增。和 u0432 u0442 u043e u0440上的 u043e u0442 u043f u0440 u0430 u0432 u043b u00a0 u044e u0442哦,实时时钟 u043c u0443 u0433 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u0435 u043a u0441 u043e u0440 u043e u043c和第一个节点,以及第一个节点和 u0432 u0442 u043e u0440之间的延迟结。在第18页的方法中,还包含一个阶段,其中为第二个节点设置了实时时钟实时时钟,相同的 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430,外加三个 u0430 u0434 u0435 u0440 u0436 u043a u0430在 u043c u0443 u043b u044c u0442 u0438 u043f u043b u043b u0435 u043a u0441 u043e u0440 u043e u043c和第一个节点,再加上第一个节点和第二个节点之间的延迟传输; 20。第19页的方法,另外包含一个阶段,其中 u0432 u0440 u0435 u0435 u043c u00a0中使用的数据多路复用器 u043e u0442 u043f u0440 u0430 u0432 u043b u00a0 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u043e m与第一节点之间的传输量,以及第一节点和第二节点传输之间的延迟。 ; 21。第15页的方法,其中包含由第一个节点内的数据内部处理引起的传输延迟。; 22。计算延迟的方法,第15页,其中 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u043e u043c与第一个节点之间的传输包括一个阶段其中时间数据与多路复用器中的第一个节点和时间之间的差异与 u043f u0440 u0438 u0431 u044b u0442 u0438 u00a0 u0438 u0437 u043c u0435 u0440 u00a0 u044e u0442 u043f u0440 u0438 u0431 u044b u0442 u0438 u00a0,使用 u0443 u0440 u0430 u0432 u043d u043d u0435 u043d u0438 u00a0。; 23计算。一种计算延迟的方法,第22页,其中,第一个节点 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u043e u043c之间的传输阶段,其中使用测得的差异,do u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u043e u043c与第一个节点之间的预期传输延迟。 24第15页的方法,还包括建立第一节点的网络地址的阶段,该网络地址等于第一个数字。25。延迟的计算方法,第17页,其中第一节点和第二节点之间的传输包括一个阶段,其中时间 u0438 u0437 u043c u0435 u0440 u00a0 u044e u0442 u043f u0440 u0438 u0431 u044b u0442来自第一个节点bw u043e u0440 u043e u0433 u043e节点的数据 u0438 u00a0和时间 u043f u0440 u0438 u0431 u044b u0442 u0438 u00a0使用 u0443 u0440 u0430 u0432 u043d u0435 u043d u0438 u00a0。; 26。在第25页的方法中,第一节点和第二节点之间的计算延迟转移还包括一个阶段,在该阶段中,p u0435 u0440 u0432 u044b u043c节点和第二节点之间使用测量的27.方法 u0434 u043b u00b0 u043c u0443 u043b u044b u044c u0442 u0438 u043f u043b u043b u0435 u043a u0441 u0441 u043e u043e u0440 u043e u043c ,第一个节点和第二个节点包含相位。将第一个实时时钟 u043c u0443 u043b u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430同步为真实小时第一个节点的时间,以及作为实时时间的小时数;从第一节点获取数据;使用 u0443 u0440 u0430 u0432 计算第一个节点与传输 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u04e u0440 u043e u043c之间的延迟u043d u0435 u043d u0438 u00a0(RTC u043a + Delay u043a)mod(MTslot)=(k-1)Tslot,其中m表示 u043f u0440 u043e u043f u043f u0443中的时间间隔数 u0441 u043a u0430 u043d u0438 u00a0环境, u0441 u043a u043e u043d u043d u0444 u0438 u0433 u0433 u0443 u0440 u0438 u0440 u043e u043e u0432 u0430 u043d u043d u043e u043e u0434 u043b u00a0在第一个节点 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u043e u043c之间的数据传输表示每个时间间隔的长度,k表示主机的地址 u0432 u0437 u00a0 u0442 u0438 u00a0 mod表示操作模块,RTC u043a表示观看真实马德里 u044c u043d u043e u0433 u043e时间第k个节点,Delay u043a表示 u043c u0443 u0的累积延迟传输第k个节点上的43b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430; u043e u0442 u043f u0440 u0430 u0432 u043b u00a0 u044e u0442第二个实时时钟 u043c u0443 u043b u044c u0442 u0438 u043f u043b u043b u0435 u043a u0441 u043e u043e u0440 u0430,第一个数字和延迟在第一个节点处点击 u0440 u0435 u0434 u0430 u0447 u0438;并建立一个等于第二时钟实时 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430的实时时钟第一节点,以及传输延迟。 ; 28。第27页的方法,另外包含一个阶段,其中 u0432 u0440 u0435 u0435 u043c u00a0中使用的数据多路复用器 u043e u0442 u043f u0440 u0430 u0432 u043b u00a0传播; 29。第27页的方法,该方法将第一实时时钟实时时钟 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430同步为第一节点实时时钟的第二个节点。 u0436 u0430 u0449 u0438 u0439哪个阶段,即 u043e u0442 u043f u0440 u0430 u0432 u043b u00a0 u044e u0442第一个实时时钟 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430,并在第一个节点上编号为1,将实时时钟中的第一个节点设置为实时的第一个小时 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430;形成第二个数字; u043e u0442 u043f u0440 u0430 u0432 u043b u00a0 u044e u0442 u043c u0443 u043b u044c u0442 u0438 u043f u043b u043b u0435 u043a u0441 u043e u043e u0440 u0430,第二个节点是第二个;并将实时时钟强加给第二个节点。作为第一个实时 u043c u0443 u043b u044c u0442 u0438 u043f u043b u0435 u043a u0441 u043e u0440 u0430。

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