method u0438u0437u0433u043eu0442u043eu0432u043bu0435u043du0438u00a0 u043cu0435u0436u0441u043eu0435u0434u0438u043du0435u043du0438u0439 integrated circuits

摘要

1.method u0438u0437u0433u043eu0442u043eu0432u043bu0435u043du0438u00a0 u043cu0435u0436u0441u043eu0435u0434u0438u043du0435u043du0438u0439 integrated circuits consisting of silicon substrate with active and passive elements and has established a dielectric layer formed over the contact u043fu043eu0434u0441u043bu043eu00a0 u0430u043bu044eu043cu0438u043du0438u00a0, causing u0430u043bu044eu043cu0438u043du0438u00a0 u0441u043bu043eu00a0 alloy with si, cu, cr, a u043cu0438u043au0440u043eu0440u0438u0441u0443u043du043au0430 u0442u0440u0430u0432u043bu0435u043du0438u0435u043c, exce u0447u0430u044eu0449u0438u0439u0441u00a0 whatin order to u043fu043eu0432u044bu0448u0435u043du0438u00a0 degree of integration and the quality of u043cu0435u0436u0441u043eu0435u0434u0438u043du0435u043du0438u0439 by u0443u043cu0435u043du044cu0448u0435u043du0438u00a0 of short circuits, u043fu043eu0434u0441u043bu043eu0439 form of u0430u043bu044eu043cu0438u043du0438u00a0 or u0430u043bu044eu043cu0438u043du0438u00a0 with u043au0440u0435u043cu043d u0438u0435u043c, thickness u043fu043eu0434u0441u043bu043eu00a0 d1 and d2 is the thickness of upper u0441u043bu043eu00a0 u0443u0434u043eu0432u043bu0435u0442u0432u043eu0440u00a0u044eu0442 u0441u043eu043eu0442u043du043eu0448u0435u043du0438u00a0u043c:;where d1 0.15 microns.;d2 0.1 microns.;the establishment of u043cu0438u043au0440u043eu0440u0438u0441u0443u043du043au0430 u043fu0440u043eu0432u043eu0434u00a0u0442 reactive ionic u0442u0440u0430u0432u043bu0435u043du0438u0435u043c plasma BCl3 laced with SiCl4 10 - 20 about.% cl2 10 - 15 of.%, 20 to 30% of n2. at a pressure of 10 to 15 pa and power density 0.6 - 0.8 w / c m2.;2. method for u043eu0442u043bu0438u0447u0430u044eu0449u0438u0439u0441u00a0 1, so that the content of copper in the upper layer of alloy u0441u043eu0441u0442u0430u0432u043bu00a0u0435u0442 0.5 to 8 mas.%.