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unterbefehlsemulation in a vliw processor
unterbefehlsemulation in a vliw processor
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机译:vliw处理器中的子命令仿真
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摘要
One embodiment of the present invention provides a system that efficiently emulates sub-instructions in a very long instruction word (VLIW) processor (101). The system operates by receiving (504) an exception condition during execution of a VLIW instruction within a VLIW program. This exception condition indicates that at least one sub-instruction within the VLIW instruction requires emulation in software or software assistance. In processing this exception condition, the system emulates the sub-instructions that require emulation in software and stores the results. The system also selectively executes (520) in hardware any remaining sub-instructions in the VLIW instruction that do not require emulation in software. The system finally combines (524) the results from the sub-instructions emulated in software with the results from the remaining sub-instructions executed in hardware, and resumes execution of the VLIW program. IMAGE
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