Processor which can conditionally inhibit trap, interrupt or exception events but inhibition means are not accessible by a running program

摘要

Disclosed is a processor with means for conditionally inhibiting trap, interrupt or exception (TIE) events. When operating under a sequence of instructions or program, the inhibition means is inaccessible by the instructions to inhibit the TIE events, without interrupting the running program. The processor may be able to configure the inhibitor during its initialisation. The inhibitor may be configured to allow the TIE event only after a privileged stack is initialised. The processor may configure the inhibitor to inhibit the TIE events when the processor is reset. The processor may configure the inhibitor when a particular type of event, such as an interrupt, is initiated. The instruction set of the processor may include a return from TIE instruction for execution during the processing of a TIE event to resume processing when the event has been completed. The inhibition means may be a portion of memory with an enable field having conditions in which the TIE events are inhibited ie disabled or allowed ie enabled.