首页> 外国专利> VERIFICATION-SCENARIO GENERATING PROGRAM, RECORDING MEDIUM RECORDING THE PROGRAM, VERIFICATION-SCENARIO GENERATING APPARATUS, AND VERIFICATION-SCENARIO GENERATING METHOD

VERIFICATION-SCENARIO GENERATING PROGRAM, RECORDING MEDIUM RECORDING THE PROGRAM, VERIFICATION-SCENARIO GENERATING APPARATUS, AND VERIFICATION-SCENARIO GENERATING METHOD

机译:验证情景生成程序,记录程序的介质,验证情景生成设备以及验证情景生成方法

摘要

PROBLEM TO BE SOLVED: To efficiently and comprehensively form a verification scenario which is needed to verify a bus system.;SOLUTION: Hardware blocks respectively of an optional access origin and an optional access destination that are mutually accessible are extracted from among a plurality of hardware blocks constituting the bus system to be verified, and a path reaching from the access-origin hardware block to the access-destination hardware block is searched for. For each path found, a verification scenario is generated to verify transactions of the access-origin hardware block for a case where access to an address range assigned to the access-destination hardware block occurs, and the verification scenario is output being correlated with the path that corresponds thereto.;COPYRIGHT: (C)2009,JPO&INPIT
机译:解决的问题:为了有效和全面地形成验证总线系统所需的验证方案。解决方案:从多个硬件中提取相互可访问的可选访问源和可选访问目的地的硬件块构成要验证的总线系统的块,并搜索从访问源硬件块到访问目的地硬件块的路径。对于找到的每个路径,在发生对分配给访问目的地硬件块的地址范围的访问的情况下,生成验证场景以验证访问源硬件块的事务,并且输出验证场景并将其与路径相关联。对应于此。;版权所有:(C)2009,JPO&INPIT

著录项

  • 公开/公告号JP2009093491A

    专利类型

  • 公开/公告日2009-04-30

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP20070264716

  • 发明设计人 RAFAEL KAZUMICHI MORIZAWA;

    申请日2007-10-10

  • 分类号G06F13/36;G01R31/28;G06F11/22;G06F13/14;G06F13/00;

  • 国家 JP

  • 入库时间 2022-08-21 19:40:52

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