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The active region which is used as the production mannered null source or

机译:用作生产习惯的空源或

摘要

Disclosed is a method for fabricating a semiconductor device including stacked capacitors on a semiconductor substrate having a logic circuit region formed with a circuit and a RAM cell region formed with a plurality of transistors, involving the steps of forming an insulating film to a thickness corresponding to a height of stacked capacitors, to be formed, over an upper surface of the semiconductor substrate, partially removing the insulating film from the RAM cell region, thereby forming a space in which the stacked capacitors are to be formed, forming the stacked capacitors in the space, and partially removing the insulating film from the logic circuit region, and forming interconnection lines for the logic circuit in a space defined in the logic circuit region by virtue of the removal of the insulating film. In accordance with this method, steps formed during the formation of capacitors are removed prior to subsequent processing steps for forming layers over those capacitors. Accordingly, it is possible to accurately pattern the layers formed after the formation of the capacitors. It is also possible to achieve a desired fineness of interconnection lines.
机译:公开了一种在包括具有由电路形成的逻辑电路区域和由多个晶体管形成的RAM单元区域的半导体基板上制造包括堆叠电容器的半导体器件的方法,该方法包括以下步骤:形成绝缘膜至对应于厚度的厚度。在半导体衬底的上表面上方形成要形成的堆叠电容器的高度,从RAM单元区域部分地去除绝缘膜,从而形成要形成堆叠电容器的空间,从而在半导体衬底中形成堆叠电容器。隔离空间,并从逻辑电路区域中部分除去绝缘膜,并通过除去绝缘膜在逻辑电路区域中限定的空间中形成用于逻辑电路的互连线。根据该方法,在随后的用于在那些电容器上形成层的处理步骤之前,去除在电容器的形成期间形成的步骤。因此,可以精确地图案化在电容器形成之后形成的层。也可以实现互连线的期望的细度。

著录项

  • 公开/公告号JP4279443B2

    专利类型

  • 公开/公告日2009-06-17

    原文格式PDF

  • 申请/专利权人 東部エレクトロニクス株式会社;

    申请/专利号JP20000300787

  • 发明设计人 金 載 甲;

    申请日2000-09-29

  • 分类号H01L21/8242;H01L27/108;

  • 国家 JP

  • 入库时间 2022-08-21 19:40:35

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