首页> 外国专利> CONTROL VOLTAGE DETERMINING METHOD OF INTEGRATED CIRCUIT, GATE VOLTAGE DETERMINING METHOD OF TEG CIRCUIT, TEG CIRCUIT TESTING METHOD AND TESTING DEVICE

CONTROL VOLTAGE DETERMINING METHOD OF INTEGRATED CIRCUIT, GATE VOLTAGE DETERMINING METHOD OF TEG CIRCUIT, TEG CIRCUIT TESTING METHOD AND TESTING DEVICE

机译:集成电路的控制电压确定方法,teg电路的门电压确定方法,teg电路的测试方法及测试装置

摘要

PPROBLEM TO BE SOLVED: To provide an integrated circuit and a TEG (Test Element Group) circuit hard to be affected by the impact on circuit operation caused by property variation or fluctuation of a transistor such as a threshold voltage. PSOLUTION: A current mode operation circuit comprises a pair of resistor devices MP1 and MP2, a pair of N type differential transistors MN1 and MN2, and a current source transistor ML for supplying operation current to the pair of N type differential transistors. The control voltage VL of the current flowing to the current source transistor is determined so that the voltage gain of the integrated circuit will become at least one or more, in relation to property variations such as the threshold voltage of the N type differential transistors. PCOPYRIGHT: (C)2009,JPO&INPIT
机译:

要解决的问题:提供一种集成电路和TEG(测试元件组)电路,该电路和TEG(测试元件组)电路不受晶体管的特性变化或波动(例如阈值电压)对电路操作的影响所影响。解决方案:电流模式运算电路包括一对电阻器器件MP1和MP2,一对N型差分晶体管MN1和MN2以及用于将工作电流提供给该对N型差分晶体管的电流源晶体管ML。确定流到电流源晶体管的电流的控制电压VL,以使集成电路的电压增益相对于诸如N型差分晶体管的阈值电压之类的特性变化变为至少一个或多个。

版权:(C)2009,日本特许厅&INPIT

著录项

  • 公开/公告号JP2008294547A

    专利类型

  • 公开/公告日2008-12-04

    原文格式PDF

  • 申请/专利权人 AGILENT TECHNOL INC;

    申请/专利号JP20070135540

  • 发明设计人 ENDO TETSUO;SASAKI KATSUTO;UTADA KAZUHISA;

    申请日2007-05-22

  • 分类号H03K19/0944;H03F3/45;G01R31/316;G01R31/26;

  • 国家 JP

  • 入库时间 2022-08-21 19:40:27

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