首页> 外国专利> COHERENT INTEGRATION ENHANCEMENT CIRCUIT, POSITIONING CIRCUIT, ELECTRONIC EQUIPMENT, COHERENT INTEGRATION ENHANCEMENT METHOD, POSITIONING METHOD, PROGRAM, AND STORAGE MEDIUM

COHERENT INTEGRATION ENHANCEMENT CIRCUIT, POSITIONING CIRCUIT, ELECTRONIC EQUIPMENT, COHERENT INTEGRATION ENHANCEMENT METHOD, POSITIONING METHOD, PROGRAM, AND STORAGE MEDIUM

机译:相干集成增强电路,定位电路,电子设备,相干集成增强方法,定位方法,程序和存储介质

摘要

PROBLEM TO BE SOLVED: To prevent an integrated value from being set off (canceled) by phase inversion of a navigation message included in a positioning satellite signal, to integrate a coherent in a phase modulation period or more of integration time.;SOLUTION: Integrated correlation values (I and Q integrated correlation values) of each of I and Q signals with an orthogonally separated received signal and a replica code are calculated by coherent integration performed by a correlation processing circuit part 32. Then, I and Q integrated correlation values are calculated by integrating further integrated phase values that are I and Q coordinate values of the integrated correlation values after converted, after phase angles θ of the integrated correlation values using the respective I and Q integrated correlation values as the I and Q coordinate values are converted into a double angle 2θ, by a coherent integration enhancement circuit 35. The in-coherent integration for the I and the Q enhancement integrated correlation values are carried out by the coherent integration enhancement circuit 35. A coherent integration time T1 by the correlation processing circuit section 32 is set to be 20 ms or less, and an integration time T2 by the coherent integration enhancement circuit part 35 is set to be longer than 20 ms.;COPYRIGHT: (C)2009,JPO&INPIT
机译:解决的问题:为了防止由于定位卫星信号中包含的导航消息的相位反转而导致积分值被抵消(抵消),以在相调周期或更长时间内积分相干。通过由相关处理电路部分32执行的相干积分来计算具有正交分离的接收信号的I和Q信号中的每一个的相关值(I和Q积分相关值)和复制码。然后,I和Q积分相关值是在相位角θ之后,通过对作为积分后的积分相关值的I和Q坐标值的其他积分相位值进行积分来计算。通过相干积分增强电路35,将分别使用I和Q积分相关值作为I和Q坐标值的积分相关值的整数转换为双角2θ。I和Q增强的非相干积分通过相干积分增强电路35对积分相关值进行积分。将相关处理电路部32的相干积分时间T1设定为20ms以下,并且将相干积分增强电路部35的积分时间T2设定为20ms以下。超过20毫秒;版权所有:(C)2009,JPO&INPIT

著录项

  • 公开/公告号JP2009002659A

    专利类型

  • 公开/公告日2009-01-08

    原文格式PDF

  • 申请/专利权人 SEIKO EPSON CORP;

    申请/专利号JP20070160914

  • 发明设计人 MURAKAMI MAKOTO;

    申请日2007-06-19

  • 分类号G01S5/14;H04B1/707;

  • 国家 JP

  • 入库时间 2022-08-21 19:39:01

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