Floor plan apparatus, floor plan program, and computer-readable recording medium recording the program

摘要

The present invention secures a degree of freedom of arrangement and wiring of internal elements of a placement target when implementing a floor plan of a semiconductor integrated circuit, and suppresses an increase in restrictions on a CAD system, while reducing the size of a semiconductor integrated circuit. In order to enable efficient realization and reduction of dead space, the floor plan apparatus is configured such that at least two placement target blocks among a plurality of placement target blocks overlap each other to form an overlapping region. A temporary placement unit (10) for temporarily placing a plurality of placement target blocks on the mounting area and an internal element of at least one placement target block among the placement target blocks forming the overlap area, using the overlap area. By changing the arrangement, an optimization unit (30) that optimizes the arrangement target block is provided.