System to Identify Timing Differences from Logic Block Changes and Associated Methods

摘要

A system to identify timing differences due to logic block changes, the system may include a controller, and storage in communication with the controller. The controller may provide delay values of a previous logic block and a current logic block. The system may also include a timing-modeler to compare the delay values of the previous logic block with the current logic block for timing analysis. The system may further include an interface that provides a report based upon the previous logic block and the current logic block comparison.