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High Speed Memory Error Detection and Correction Using Interleaved (8,4) LBCs
High Speed Memory Error Detection and Correction Using Interleaved (8,4) LBCs
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机译:使用交错(8,4)LBC进行高速存储器错误检测和纠正
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摘要
Methods and systems are disclosed for the detection and correction of memory errors using code words with a quantity, divisible by 4, of data bits, with an equal quantity of check bits, and having the check bits and data bits interleaved. Upon execution of a memory write instruction, a processor may send a memory word to a check bit generator that generates the check bits before the code word is written to a memory unit. Upon a signal from the processor that a memory read is requested, the memory unit may send a stored code word to a syndrome bit generator to generate a syndrome vector. The syndrome vector may then be sent to a correction bit generator and an uncorrectable error detector. These units may send corrected bits and an uncorrectable error signal, respectively, to the processor.
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