首页>
外国专利>
Design Structure for Glitchless Clock Multiplexer Optimized for Synchronous and Asynchronous Clocks
Design Structure for Glitchless Clock Multiplexer Optimized for Synchronous and Asynchronous Clocks
展开▼
机译:针对同步和异步时钟优化的无毛刺时钟多路复用器的设计结构
展开▼
页面导航
摘要
著录项
相似文献
摘要
A design structure for a circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The design structure comprises a circuit having an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency (period in which no clock pulse appears at the final output of the circuit) from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal.
展开▼