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Method and system to optimize timing margin in a system in package module
Method and system to optimize timing margin in a system in package module
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机译:在封装模块中的系统中优化时序裕度的方法和系统
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摘要
In a System-in-Package (SiP) module, a method and a system for optimizing the timing margin of source-synchronous interface clocks is provided. Clock signals generated by first device are transmitted to serpentine traces located on a Printed Circuit Board (PCB) which adjusts the active edge of one signal relative to another signal. The serpentine trace introduces a delay in the clock signal thereby optimizing timing margins. By providing access to signals otherwise internal the SiP, testing and signal verification is also simplified.
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