Circuit analysis utilizing rank revealing factorization

摘要

Method of forming a reduced model of a circuit. A circuit parameter is selected, and a plurality of values for the parameter are selected. A circuit or operator equation is solved for the selected plurality of values to generate a result. The acts of selecting parameter and its plurality of values and solving the equation are repeated to generate sufficient results to form a reduced model. For each iteration, a rank revealing factorization is performed on the matrix for use in determining whether a sufficient number of results or vectors have been generated to form the reduced model so as to form a reduced model. In the plurality of values for a selected parameter, there may exist large deviation between two of the plurality of values for a selected parameter, and such deviation need not be based upon a nominal point or deviation thereof.