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Systems and Methods for Testing and Diagnosing Delay Faults and For Parametric Testing in Digital Circuits

机译:用于测试和诊断延迟故障以及数字电路中的参数测试的系统和方法

摘要

Delay-fault testing and parametric analysis systems and methods utilizing one or more variable delay time-base generators. In embodiments of the delay-fault testing systems, short-delay logic paths are provided with additional scan-chain memory elements and logic that, in conjunction with the one or more variable-delay time-base generators, provides the effect of over-clocking without the need to over-clock. Related methods provide such effective over-clocking. In embodiments of parametric analysis systems, test point sampling elements and analysis circuitry are clocked as a function of the output of the one or more variable-delay time-base generators to provide various parametric analysis functionality. Related methods address this functionality.
机译:利用一台或多台可变延迟时基发生器的延迟故障测试和参数分析系统及方法。在延迟故障测试系统的实施例中,短延迟逻辑路径设置有附加的扫描链存储元件和逻辑,该逻辑与一个或多个可变延迟时基生成器一起提供超频效果无需超频。相关方法可提供有效的超频功能。在参数分析系统的实施例中,根据一个或多个可变延迟时基发生器的输出来对测试点采样元件和分析电路进行计时,以提供各种参数分析功能。相关方法解决了此功能。

著录项

  • 公开/公告号US2009198461A1

    专利类型

  • 公开/公告日2009-08-06

    原文格式PDF

  • 申请/专利权人 MOHAMED M. HAFED;

    申请/专利号US20080026760

  • 发明设计人 MOHAMED M. HAFED;

    申请日2008-02-06

  • 分类号G01R29/26;G06F11/00;G06F19/00;

  • 国家 US

  • 入库时间 2022-08-21 19:32:26

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