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Gate-level netlist reduction for simulating target modules of a design
Gate-level netlist reduction for simulating target modules of a design
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机译:门级网表简化,用于仿真设计的目标模块
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摘要
A method for analyzing a circuit design in preparation for a simulation. The method generally includes the steps of (A) marking each of a plurality of modules between a target module of the modules and a top module of the modules in a hierarchy of the circuit design as a first type by traversing upward through the hierarchy starting from the target module, (B) marking each of the modules as a second type where a parent module of the modules is marked as the first type by traversing downward through the hierarchy starting from the top module and (C) marking each of the modules as a third type where the parent module is not marked as the keep type by traversing downward through the hierarchy starting from the top module.
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