首页> 外国专利> MULTI-TAP DECISION FEEDBACK EQUALIZER (DFE) ARCHITECTURE ELIMINATING CRITICAL TIMING PATH FOR HIGHER-SPEED OPERATION

MULTI-TAP DECISION FEEDBACK EQUALIZER (DFE) ARCHITECTURE ELIMINATING CRITICAL TIMING PATH FOR HIGHER-SPEED OPERATION

机译:多TAP决策反馈均衡器(DFE)体系结构消除了加快操作速度的关键时序

摘要

A decision feedback equalizer (DFE) and method include summer circuits to add a dynamic feedback signal representing a dynamic feedback tap to a received input and to speculate on a speculative tap. Data slicers are configured to receive outputs of the summer circuits and sample the outputs of the summer circuits. First multiplexers are included, each of which is configured to receive a first input from a corresponding data slicer. Second multiplexers are included, each of which is configured to receive an output of a plurality of the first multiplexers. The second multiplexers have an output fed back to a second input of the first multiplexers, and the second multiplexer output is employed to provide a select signal for a second multiplexer on a different section of the DFE and to drive the dynamic feedback signal to a summer circuit on a same section of the DFE.
机译:决策反馈均衡器(DFE)和方法包括求和电路,用于将表示动态反馈抽头的动态反馈信号添加到接收的输入,并推测投机抽头。数据限幅器配置为接收求和电路的输出并采样求和电路的输出。包括第一多路复用器,每个第一多路复用器被配置为从相应的数据限幅器接收第一输入。包括第二多路复用器,每个第二多路复用器被配置为接收多个第一多路复用器的输出。第二多路复用器的输出反馈到第一多路复用器的第二输入,并且第二多路复用器输出用于为DFE的不同部分上的第二多路复用器提供选择信号,并将动态反馈信号驱动到求和器DFE同一部分上的电路。

著录项

  • 公开/公告号US2009060021A1

    专利类型

  • 公开/公告日2009-03-05

    原文格式PDF

  • 申请/专利权人 JOHN F. BULZACCHELLI;

    申请/专利号US20070848477

  • 发明设计人 JOHN F. BULZACCHELLI;

    申请日2007-08-31

  • 分类号H04L27/22;H03D3/22;

  • 国家 US

  • 入库时间 2022-08-21 19:31:35

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