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MODELING ASYNCHRONOUS BEHAVIOR FROM PRIMARY INPUTS AND LATCHES
MODELING ASYNCHRONOUS BEHAVIOR FROM PRIMARY INPUTS AND LATCHES
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机译:从原始输入和锁存中模拟异步行为
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摘要
Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from the driving element, (ii) a delayed output from the driving element, or (iii) a random value, which drives downstream logic. The output of the additional logic is selectively responsive to a user-controlled skew enable input. The invention allows for simpler data skew logic transformations which are applicable to both latches and primary inputs, with no dependencies on any clock net.
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