STRUCTURE FOR REDUCING COHERENCE ENFORCEMENT BY SELECTIVE DIRECTORY UPDATE ON REPLACEMENT OF UNMODIFIED CACHE BLOCKS IN A DIRECTORY-BASED COHERENT MULTIPROCESSOR

摘要

A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design to reduce the number of memory directory updates during block replacement in a system having a directory-based cache is provided. The design structure may be implemented to utilize a read/write bit to determine the accessibility of a cache line and limit memory directory updates during block replacement to regions that are determined to be readable and writable by multiple processors.