首页>
外国专利>
Cache coherency control method, chipset, and multi-processor system
Cache coherency control method, chipset, and multi-processor system
展开▼
机译:高速缓存一致性控制方法,芯片组和多处理器系统
展开▼
页面导航
摘要
著录项
相似文献
摘要
In a multi-processor system, counting snoop results bottlenecks the broadcast-based snoop protocol. The directory-based protocol delays the latency when remote node caches data. There is a need for shortening the memory access latency using a snoop and cache copy tag information. When the local node's cache copy tag information is available, the memory access latency can be shortened by omitting a process to count snoop results. When memory position information is used to update the cache copy tag during cache replacement, it is possible to increase a ratio to hit a copy tag during reaccess from the local node.
展开▼