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Multi-hit control method for shared TLB in a multiprocessor system

机译:多处理器系统中共享TLB的多点击控制方法

摘要

The present invention comprises, for enabling sharing an address translation buffer (TLB=Translation Lookaside Buffer) between plural threads without generating undesirable multi-hits in an information processor which operates in multi-thread mode, an address translation buffer for storing address translation pairs and thread information, a retriever for retrieving an address translation pair of a virtual addresses identical to said virtual address from the address translation buffer for translating the virtual address into a physical address, a determination unit for determining, when plural addresses translation pairs are retrieved by the retriever, whether or not two or more of said thread information are identical among plural thread information corresponding to plural address translation pairs, and a multi-hit controller for suppressing output of multi-hits and directing execution of address translation if the thread information are determined to be different according to the determination unit.
机译:本发明包括用于在多个线程之间共享地址转换缓冲器(TLB =转换后备缓冲器)而不会在以多线程模式操作的信息处理器中产生不希望的多重命中的情况,该地址转换缓冲器用于存储地址转换对和线程信息,检索器,用于从用于将虚拟地址转换为物理地址的地址转换缓冲器中检索与所述虚拟地址相同的虚拟地址的地址转换对,确定单元,用于确定何时由多个地址转换对检索到多个地址转换对。检索器,在对应于多个地址翻译对的多个线程信息中,所述线程信息中的两个或多个是否相同,以及如果确定了线程信息,则用于抑制多重命中的输出并指导地址翻译的执行的多重命中控制器。根据实际情况有所不同消除单元。

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