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Determining a time difference between first and second clock domains
Determining a time difference between first and second clock domains
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机译:确定第一和第二时钟域之间的时间差
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摘要
Buffer circuitry receives data to be processed by electronic circuitry using a first clock signal associated with a first clock domain. The buffered data is output using a second clock signal associated with a second clock domain. The buffering of the data is associated with a buffering delay. Counting circuitry receives at a start count input a write timing signal associated with the first clock domain and with writing data to the buffer circuitry. The counting circuitry receives at a stop count input a read timing signal associated with the second clock domain and with reading data from the buffer circuitry. A count value accumulated between receiving the write timing signal and the read timing signal corresponds to the buffering delay. Control circuitry performs a control operation based on the count value.
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